CMOS imager with focal-plane image compression based on the EZW algorithm

We present the design of a focal-plane image compression circuit for CMOS cameras. Data compression is obtained by the analog hardware implementation of a lossy algorithm based on wavelet theory and employing zerotree data structures to classify and discard irrelevant information at reduced bandwidth cost. An image sensor with resolution 32 × 32 containing the image processing circuits was designed with 0.35 μm technology. Electrical simulations which consider the CMOS fabrication process variations in accordance to the parameters provided by the foundry were carried out and the results are compared with a system-level numerical simulation of the proposed algorithm. The proposed circuit implementation achieves compression ratio around 3:1 through an iterative process which progressively reduces image resolution. The corresponding image quality (peak signal-to-noise ratio) is around 22.2 dB in Monte Carlo electrical simulations.