DocumentCode
1432193
Title
A high-speed residue-to-binary converter for three-moduli (2k , 2k-1, 2k-1-1) RNS and a scheme for its VLSI implementation
Author
Wang, Wei ; Swamy, M.N.S. ; Ahmad, M.O. ; Wang, Yuke
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Volume
47
Issue
12
fYear
2000
fDate
12/1/2000 12:00:00 AM
Firstpage
1576
Lastpage
1581
Abstract
In this paper, a high-speed residue-to-binary converter for the moduli set (2k, 2k-1, 2k-1-1) is proposed. Compared to the previous converter based on this moduli set, the proposed one is 40% faster. Also, the time-complexity product is improved by 20%. Following the top-down very large scale integration design flow, the proposed converter is implemented in 0.5 micron CMOS technology. Based on this moduli set, layouts of the 8-, 16-, 32-, and 64-bit residue-to-binary converters, which can be used in further residue number system designs, are generated and simulation results obtained
Keywords
CMOS digital integrated circuits; VLSI; convertors; digital signal processing chips; high-speed integrated circuits; integrated circuit layout; residue number systems; DSP; VLSI implementation; high-speed residue-to-binary converter; residue number system designs; submicron CMOS technology; three-moduli RNS; time-complexity product improvement; top-down VLSI design flow; very large scale integration; CMOS technology; Cathode ray tubes; Circuits; Computer science; Councils; Digital filters; Digital signal processing; Information management; Signal processing; Very large scale integration;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.899659
Filename
899659
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