DocumentCode
1432263
Title
Rearrangeable operation of large crosspoint switching networks
Author
Varma, Anujan ; Ghosh, Joydeep ; Georgiou, Christos J.
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume
38
Issue
9
fYear
1990
fDate
9/1/1990 12:00:00 AM
Firstpage
1616
Lastpage
1624
Abstract
A major impediment to building large crosspoint chips for configuring crosspoint switching networks is the simultaneous switching (Delta-I ) noise problem that is caused by the switching of a large number of line drivers driving the output pins of the package. This limits the size of the largest crosspoint chips that can be operated reliably. An architectural solution to this problem is presented for networks constructed from one-sided crosspoint switching chips. The approach seeks to minimize the maximum number of active drivers in the individual chips by distributing the active drivers in the network uniformly among the chips by allowing rearrangements of existing connections when a new connection is made. A graph model is used to determine the number and location of rearrangements. An allocation scheme based on a simplified graph model that achieves a 50% reduction in the maximum number of active drivers per chip as compared to a random allocation strategy is presented. A maximum of three rearrangements is sufficient to obtain this reduction
Keywords
graph theory; switching networks; Delta-I noise reduction; active driver distribution; allocation scheme; crosspoint chips; graph model; large crosspoint switching networks; one-sided architecture; rearrangeable operation; simultaneous-switching noise; Artificial intelligence; Circuit noise; Communication switching; Driver circuits; Impedance; Multiprocessor interconnection; Packaging; Pins; Switches; Very large scale integration;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/26.61404
Filename
61404
Link To Document