DocumentCode :
1432567
Title :
0.5-6 ghz low-voltage low-power mixer using a modified cascode topology in 0.18 μm cmos technology
Author :
Liang, K.-H. ; Chang, Hong-Yeh
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan
Volume :
5
Issue :
2
fYear :
2011
Firstpage :
167
Lastpage :
174
Abstract :
A broadband low-voltage low-power down-conversion mixer using a 0.18 m standard CMOS process is presented. The proposed mixer uses a modified cascode topology with a bulk-injection technique to achieve low-voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency (RF) of 2.4 GHz, a single-sideband (SSB) noise figure of 15.2 dB, and an input third-order intercept point (IIP3) of 0 dBm. Moreover, the chip area of the mixer core is only 0.15 0.23 mm2. The measured 3 dB RF bandwidth is from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (VDD) can be scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be compatible with an advanced 90 or 65 nm CMOS technology.
Keywords :
CMOS integrated circuits; UHF mixers; microwave mixers; CMOS technology; DC power; RF bandwidth; broadband low-voltage low-power down-conversion mixer; bulk-injection technique; current 0.4 mA; frequency 0.5 GHz to 6 GHz; frequency 100 MHz; input third-order intercept point; low-voltage low-power mixer; mixer core chip area; modified cascode topology; noise figure 15.2 dB; optimum DC supply voltage; single-sideband noise figure; standard CMOS process;
fLanguage :
English
Journal_Title :
Microwaves, Antennas & Propagation, IET
Publisher :
iet
ISSN :
1751-8725
Type :
jour
DOI :
10.1049/iet-map.2009.0292
Filename :
5697294
Link To Document :
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