Hardware design of FFT polynomial multipliers

Author

Renteria-Mejia, C.P. ; Lopez-Parrado, Alexander ; Velasco-Medina, J.

Author_Institution

Bionanoelectronics Res. Group, Univ. del Valle, Cali, Colombia

fYear

2014

fDate

25-28 Feb. 2014

Firstpage

1

Lastpage

4

Abstract

This paper presents the design of two FFT polynomial multipliers using parallel and sequential architectures. Parallel and sequential polynomial multipliers were optimized for throughput and area resources, respectively. The designs are described in generic structural VHDL, synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for high-performance scientific computing applications.

Keywords

fast Fourier transforms; hardware description languages; logic design; multiplying circuits; parallel architectures; FFT polynomial multipliers; Quartus II V 13; SignalTap; Stratix EP4SGX230KF40C2; VHDL; area resources; area-throughput; hardware design; hardware synthesis; high-performance scientific computing applications; parallel architectures; parallel polynomial multipliers; sequential architectures; sequential polynomial multipliers; Clocks; Hardware; Mathematical model; Polynomials; Random access memory; Software; Throughput; FFT; FPGAs; hardware design; polynomial multiplication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2014 IEEE 5th Latin American Symposium on

Conference_Location

Santiago

Print_ISBN

978-1-4799-2506-3

Type

conf

DOI

10.1109/LASCAS.2014.6820315

Filename

6820315