A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges

Based on the perimeter-weighted-sum method and scaling theory, a compact threshold voltage model for surrounding-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows how various charge conditions such as the positive/negative trapped charges and device structure parameters such as the silicon thickness, oxide thickness, and channel length affect the threshold voltage behavior. The model is verified by the 3-D device simulator and can be efficiently used to explore hot-carrier-induced threshold voltage degradation of the charge-trapped memory device.