Title :
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Author :
Hur, J.Y. ; Stefanov, Todor ; Wong, Simon ; Goossens, Kees
Author_Institution :
Comput. Eng. Lab., Tech. Univ. Delft, Delft, Netherlands
fDate :
1/1/2012 12:00:00 AM
Abstract :
Conventional rigid and general purpose on-chip networks occupy significant logic and wire resources in field-programmable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, where physical topologies are identical to logical topologies for a given application. A multiprocessor system combined with the presented custom crossbar has been designed with the ESPAM design environment and prototyped in the FPGA device. Experiments with practical applications show that the custom crossbar occupies significantly less area, maintains higher performance and reduces the power consumption, when compared with the general-purpose crossbars. In addition, the authors present that configuration performance and cost can be improved by reducing the functional area cost in FPGAs. Second, a customisation technique for the circuit-switched network-on-chip (NoC) is presented, where only necessary half-duplex interconnects are established for a given application mapping. The presented customised NoC is implemented in FPGA and results indicate that the area is reduced by 66%, when compared with the general-purpose networks.
Keywords :
circuit switching; electronic switching systems; field programmable gate arrays; logic design; multiprocessor interconnection networks; network topology; network-on-chip; power aware computing; reconfigurable architectures; ESPAM design environment; FPGA; NoC; area cost reduction; circuit-switched network-on-chip; customised crossbar switch design; field programmable gate arrays; general purpose on-chip networks; half-duplex interconnects; logical topology; multiprocessor system; on-chip network interconnect customisation; on-demand network interconnects; power consumption reduction; reconfigurable hardware; topology customisation technique;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt.2010.0105