Establishing Best-Practice Modeling Approaches for Understanding Single-Event Transients in Gb/s SiGe Digital Logic

Single-event transient (SET) simulations of a Gb/s SiGe BiCMOS master/slave D flip-flop circuit are performed, employing both a decoupled current-injection SET modeling technique and a fully-coupled mixed-mode TCAD technique to model heavy-ion strikes to the storage and input cells. New insights are provided into the physical mechanisms underlying the single-event upset (SEU) sensitivity of high-speed SiGe digital latches and shift registers. A close analysis of the transient circuit behavior identifies the limitations of the current-injection approach in predicting SEU in fast SiGe digital logic. Furthermore, the physical ion track linear energy transfer (LET) is varied to establish the threshold LET for SEU using each simulation technique, further highlighting the SEU prediction error inherent to conventional decoupled modeling approaches. Finally, clocked mixed-mode circuit simulations are used to explain the fundamental SEU mechanisms and relate them to corresponding regions of the device-level SET.