Title :
A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter
Author :
Sutarja, Sehat ; Gray, Paul R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
12/1/1988 12:00:00 AM
Abstract :
A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3-μm, CMOS technology. Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize the overall cost. The prototype converter requires 3400 mil2, and consumes 15 mW
Keywords :
CMOS integrated circuits; analogue-digital conversion; 13 bit; 15 mW; 3 micron; 5 V; CMOS technology; cost; monotonicity; pipelined A/D convertor; prototype converter; reference-feedforward correction; Analog-digital conversion; CMOS process; CMOS technology; Calibration; Clocks; Cost function; ISDN; Laboratories; Prototypes; Signal processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
