DocumentCode :
1434035
Title :
Impacts of Multiple-Gated Configuration on the Characteristics of Poly-Si Nanowire SONOS Devices
Author :
Hsu, Hsing-Hui ; Lin, Horng-Chih ; Luo, Cheng-Wei ; Su, Chun-Jung ; Huang, Tiao-Yuan
Author_Institution :
Dept. of Electron. Eng. & Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
58
Issue :
3
fYear :
2011
fDate :
3/1/2011 12:00:00 AM
Firstpage :
641
Lastpage :
649
Abstract :
In this paper, we have proposed a simple and novel way to fabricate poly-Si nanowire (NW)-silicon-oxide-nitride-oxide-silicon (SONOS) devices with various gate configurations. Three types of devices having various gate configurations, such as side gated, -shaped gated , and gate-all-around (GAA), were successfully fabricated and characterized. The experimental results show that, owing to the superior gate controllability over NW channels, much improved transfer characteristics are achieved with the GAA devices, as compared with the other types of devices. Moreover, GAA devices also exhibit the best memory characteristics among all splits, including the fastest programming/erasing efficiency, largest memory window, and best endurance/retention characteristics, highlighting the potential of such scheme for future SONOS applications.
Keywords :
flash memories; nanowires; nitrogen compounds; silicon compounds; GAA devices; NW channels; Si; SiO-NO-Si; endurance-retention characteristics; memory window; multiple-gated configuration; poly-Si nanowire SONOS devices; Field-effect transistor (FET); multiple gate (MG); nanowire (NW); poly-Si; silicon-oxide-nitride-oxide-silicon (SONOS);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2010.2098033
Filename :
5699915
Link To Document :
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