Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High- $k$ Dielectrics

Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si_{1 -} x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si_{1 -} x Gex thicknesses, boron counterdopings, and gate work functions.