Title :
10 K-gate GaAs JFET sea of gates
Author :
Kawasaki, Hidetoshi ; Wada, Masaru ; Hida, Yukio ; Takano, Chiaki ; Kasahara, Jiro
Author_Institution :
Sony Corp. Res. Center, Yokohama, Japan
fDate :
10/1/1991 12:00:00 AM
Abstract :
The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 μm. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively
Keywords :
III-V semiconductors; field effect integrated circuits; gallium arsenide; invertors; junction gate field effect transistors; logic arrays; 0.5 micron; CMOS levels; T-type flip-flop; TTL levels; direct coupled FET logic; emitter-coupled-logic; enhancement-type JFET; four-NOR circuit; gate delays; gate length; inverter circuit; junction FETs; power consumption; sea of gates; source coupled FET logic; toggle frequency; CMOS logic circuits; Coupling circuits; Delay; Energy consumption; FETs; Gallium arsenide; JFET circuits; Logic circuits; Logic design; Pulse inverters;
Journal_Title :
Solid-State Circuits, IEEE Journal of
