A 9-ns, 1.4-gigabyte/s, 17-ported CMOS register file

Author

Jolly, Richard D.

Author_Institution

Intel. Corp., Hillsboro, OR, USA

Volume

26

Issue

10

fYear

1991

fDate

10/1/1991 12:00:00 AM

Firstpage

1407

Lastpage

1412

Abstract

Advances in circuit and microarchitecture design have made it possible to develop a 9-ns, 17-ported register file which can support a full 1.4-gigabyte/s bandwidth. With 79000 transistors in a 1-μm CHMOS process, the 4 K register file is a major unit of a microprocessor, which is a 100-MOPS VLSI parallel processing component with an integrated communication unit. The benefit of increased system performance is realized since all connected functional units can receive full bandwidth operand supply. A brief introduction gives a conceptual framework to understand the architecture and bandwidth implications. Various techniques were used to optimize the macroarchitecture by modifying the register file´s internal microarchitecture. All aspects of the design including read/write circuitry, cell stability, and special access cells are described

Keywords

CMOS integrated circuits; buffer storage; file organisation; memory architecture; 1 micron; 1.4 Gbyte/s; 9 ns; CHMOS process; access cells; cell stability; full bandwidth operand supply; internal microarchitecture; microarchitecture design; read/write circuitry; Bandwidth; Circuit synthesis; Computer architecture; Concurrent computing; Frequency; Microprocessors; Registers; Signal processing; Switches; System-on-a-chip;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.90095

Filename

90095