A reconfigurable wafer-scale memory

Author

Boubekeur, Ahmed ; Saucier, Gabrièkle ; Trilhe, Jacques

Author_Institution

Lab. Conception de Syst. Integres, Inst. Nat. Polytech. de Grenoble, France

Volume

26

Issue

10

fYear

1991

fDate

10/1/1991 12:00:00 AM

Firstpage

1423

Lastpage

1432

Abstract

Describes the design and experimental results of a wafer-scale reconfigurable static memory. To achieve this, elementary memory chips are implemented on a 4-in wafer with a regular layout allowing step-and-repeat manufacturing, and the final memory is constructed with the good chips. After an external test, a cartography of good chips is established. Two algorithms, one based on distance sorting and the other one on a linear scanning of the wafer, have been developed to define an optimized global architecture with the good chips. Hard configuration of these chips is done by laser techniques. The switching technology to discard faulty elements and replace them by spares and the copper tracks to drive a large amount of current on typical 10-cm lines are described

Keywords

VLSI; integrated memory circuits; memory architecture; cartography; distance sorting; faulty elements; laser techniques; linear scanning; memory chips; optimized global architecture; reconfigurable wafer-scale memory; static memory; step-and-repeat manufacturing; switching technology; CMOS technology; Circuit faults; Decoding; Image storage; Manufacturing; Power system reliability; Random access memory; Sorting; Testing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.90097

Filename

90097