High-speed on-chip ECC for synergistic fault-tolerance memory chips

Author

Fifield, J.A. ; Stapper, C.H.

Author_Institution

IBM Gen. Technol. Div., Essex Junction, VT, USA

Volume

26

Issue

10

fYear

1991

fDate

10/1/1991 12:00:00 AM

Firstpage

1449

Lastpage

1452

Abstract

The placement of error-correcting-code (ECC) systems on dynamic-RAM (DRAM) chips poses many practical problems, among which are increased access time and chip size. The authors describe an optimized, self-contained, and self-timed on-chip ECC system embedded in a high-speed 16-Mb DRAM chip. This chip also has redundant word and bit lines. The combination of redundancy and on-chip ECC produces a synergistic effect which results in a major increase in fault tolerance for the hard manufacturing defects. It also improves the reliability of the chip, regardless of manufacturing defects. This improvement is attained with only a 5-ns penalty in access time and an 11% increase in chip size

Keywords

DRAM chips; circuit reliability; error correction codes; 16 Mbit; DRAMs; access time; chip size; error-correcting-code; hard manufacturing defects; on-chip ECC; redundant bit lines; redundant word lines; reliability; synergistic fault-tolerance memory chips; Circuit testing; Delay; Error correction codes; Fault tolerance; Logic; Random access memory; Redundancy; Switches; System-on-a-chip; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.90100

Filename

90100