Capacitance of semiconductor p-n junction space-charge layers: an overview

The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide)