Title :
Virtual address cache with no reverse address buffering
Author :
Lopriore, Lanfranco
Author_Institution :
Istituto di Elaborazione della Inf., Pisa, Italy
fDate :
11/1/1988 12:00:00 AM
Abstract :
A virtual address cache memory, whose operation is controlled explicitly by software, is presented. Ad hoc hardware mechanisms, including machine instructions and an operand addressing mode, reduce the complexity of cache management logic in favor of the capacity of the cache, and solve the major problem of virtual address cache organization: two or more virtual addresses mapping into the same real address
Keywords :
buffer storage; controlled explicitly by software; machine instructions; no reverse address buffering; operand addressing mode; operation; organization; virtual address cache memory; Cache memory; Cache storage; Councils; Hardware; Logic devices; Memory management; Production; Space technology; Upper bound; Waste management;
Journal_Title :
Proceedings of the IEEE
