CMOS buffer sizing for long on-chip interconnects

A novel transistor sizing rule for long interconnect drivers is proposed. It allows true line matching to be achieved, thus either minimising delay or preserving signal integrity, when propagation time along the line becomes significant with respect to signal transition time. In this case the transmission line properties of long interconnects alter the behaviour of the CMOS buffer, forcing transistors to work mainly in the linear mode rather than in saturation as is usually assumed