• DocumentCode
    1435917
  • Title

    Characteristics of a Novel Compliant Bump for 3-D Stacking With High-Density Inter-Chip Connections

  • Author

    Watanabe, Naoya ; Asano, Tanemasa

  • Author_Institution
    Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka, Japan
  • Volume
    1
  • Issue
    1
  • fYear
    2011
  • Firstpage
    83
  • Lastpage
    91
  • Abstract
    This paper reports on the detailed characteristics of a novel compliant bump for 3-D stacking with high-density inter-chip connections. The novel compliant bump is a cone-shaped bump made of Au. It is fabricated using electroplating of the Au into undercut holes formed in a photoresist. Because the cone bump is easily deformed under a pressing load, it possesses superior properties for inter-chip connection. First, it suppresses a bonding failure by compensating for the bump-height deviation and the nonuniform bonding pressure, and consequently, offers high-density inter-chip connections of which number is at least 30 600 with 20 μm pitch. Second, it reduces the change in the transconductance gm of the metal-oxide-semiconductor field effect transistor (MOSFET) after chip stacking. In other words, it reduces the strain generation at the Si device level. Third, room-temperature bonding is achieved by mechanical caulking between the cone bumps and the doughnut-shaped electrodes.
  • Keywords
    MOSFET; bonding processes; electrochemical electrodes; electroplating; gold; integrated circuit interconnections; photoresists; pressing; stacking; 3D stacking; Au; bonding pressure; bump-height deviation; chip stacking; compliant bump; cone-shaped bump; doughnut-shaped electrode; electroplating; high-density interchip connection; mechanical caulking; metal-oxide-semiconductor field effect transistor; photoresist; strain generation; temperature 293 K to 298 K; transconductance; 3-D LSI; 3-D integration; 3-D stacking; Compliant bump; compliant interconnection; cone bump; flip-chip bonding; high-density inter-chip connections; metal–oxide–semiconductor field effect transistor (MOSFET) degradation; pyramid bump; room-temperature bonding; undercut resist method;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    2156-3950
  • Type

    jour

  • DOI
    10.1109/TCPMT.2010.2101450
  • Filename
    5701785