Title :
Technique for high speed asynchronous pipeline control
Author :
Appleton, S.S. ; Morton, S.V. ; Liebelt, M.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Adelaide Univ., SA, Australia
fDate :
10/10/1996 12:00:00 AM
Abstract :
The authors explore the potential for enhanced performance in asynchronous pipeline control, by eliminating unneccessary signalling in bounded-delay asynchronous systems. An improvement of 15 and 36% in cycle time over optimal two and four phase asynchronous dynamic logic implementations, respectively, is demonstrated
Keywords :
asynchronous circuits; integrated logic circuits; logic design; pipeline processing; bounded-delay asynchronous systems; cycle time; high speed asynchronous pipeline control;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19961308
