• DocumentCode
    1436694
  • Title

    Embedded DRAM in 45-nm Technology and Beyond

  • Author

    Anand, Darren L. ; Gorman, Kevin W. ; Jacunski, Mark D. ; Paparelli, Adrian J.

  • Author_Institution
    Microelectron. Div., IBM, Essex Junction, VT, USA
  • Volume
    28
  • Issue
    1
  • fYear
    2011
  • Firstpage
    14
  • Lastpage
    21
  • Abstract
    As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.
  • Keywords
    DRAM chips; memory architecture; SRAM; eDRAM architecture; embedded DRAM; embedded memories; high-performance microprocessors; size 45 nm; DRAM; and fault tolerance; cache memories; design and test; design styles; diagnostics; error checking; redundant design; reliability; semiconductor memories; test generation; testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2011.2
  • Filename
    5703064
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1436694