Title :
Embedded DRAM in 45-nm Technology and Beyond
Author :
Anand, Darren L. ; Gorman, Kevin W. ; Jacunski, Mark D. ; Paparelli, Adrian J.
Author_Institution :
Microelectron. Div., IBM, Essex Junction, VT, USA
Abstract :
As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.
Keywords :
DRAM chips; memory architecture; SRAM; eDRAM architecture; embedded DRAM; embedded memories; high-performance microprocessors; size 45 nm; DRAM; and fault tolerance; cache memories; design and test; design styles; diagnostics; error checking; redundant design; reliability; semiconductor memories; test generation; testing;
Journal_Title :
Design & Test of Computers, IEEE
