DocumentCode
1436980
Title
Analysis of improved adiabatic pseudo-domino logic family
Author
Patel, D.C. ; Morton, E.J.
Author_Institution
Dept. of Electron., Surrey Univ., Guildford, UK
Volume
34
Issue
19
fYear
1998
fDate
9/17/1998 12:00:00 AM
Firstpage
1829
Lastpage
1830
Abstract
The authors show that when an improved adiabatic pseudo-domino logic circuit is used to perform complex logic, the circuit is susceptible to switching noise and logic failure
Keywords
CMOS logic circuits; failure analysis; logic CAD; adiabatic pseudo-domino logic family; complex logic; logic failure; switching noise;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19981311
Filename
722361
Link To Document