DocumentCode :
1437001
Title :
Two-phase back-bias generator for low-voltage gigabit DRAMs
Author :
Kim, Y.H. ; Park, Hyung Jo ; Sohn, J.D. ; Choi, J.S. ; Park, C.S. ; Ahn, S.H. ; Jeong, J.Y.
Author_Institution :
Pohang Univ. of Sci. & Technol., South Korea
Volume :
34
Issue :
19
fYear :
1998
fDate :
9/17/1998 12:00:00 AM
Firstpage :
1831
Lastpage :
1833
Abstract :
A two-phase back-bias (VBB) generator is proposed for use in gigabit DRAMs using triple-well CMOS technology. The lower limit of VCC for the proposed VBB generator is a single VT (threshold voltage), whereas that for the conventional generator is 2-Vp
Keywords :
CMOS memory circuits; DRAM chips; pulse generators; low-voltage gigabit DRAMs; threshold voltage; triple-well CMOS technology; two-phase back-bias generator;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19981332
Filename :
722364
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1437001
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