Title :
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
Author :
Zarkesh-Ha, Payman ; Davis, Jeffrey A. ; Meindl, James D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
A system-on-a-chip (SoC) contains several pre-designed heterogeneous megacells that have been designed and routed optimally. In this paper a new stochastic net-length distribution for global interconnects in a nonhomogeneous SoC is derived using novel models for netlist, placement, and routing information. The netlist information is rigorously derived based on heterogeneous Rent´s rule, the placement information is modeled by assuming a random placement of terminals for a given net in a bounding area, and the routing information is constructed based on a new model for minimum rectilinear Steiner tree construction (MRST). The combination of the three models gives a priori estimation of global net-length distribution in a heterogeneous SoC. Unlike previous models that empirically relate the average length of the global wires to the chip area, the new distribution provides a complete and accurate distribution of net-length for global interconnects. Through comparison with actual product data, it is shown that the new stochastic model successfully predicts the global net-length distribution of a heterogeneous system.
Keywords :
VLSI; application specific integrated circuits; cellular arrays; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; network routing; trees (mathematics); Rent´s rule; VLSI; bounding area; global interconnects; global net-length distribution; global wires; heterogeneous system-on-a-chip; megacells; minimum rectilinear Steiner tree construction; netlist information; nonhomogeneous SoC; optimal routing; placement information; routing information; stochastic net-length distribution; Design automation; Frequency estimation; Predictive models; Routing; Stochastic processes; Stochastic systems; System-on-a-chip; Timing; Wire; Wiring;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on