A compact physical via blockage model

Author

Chen, Qiang ; Davis, Jeffrey A. ; Zarkesh-Ha, Payman ; Meindl, James D.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

8

Issue

6

fYear

2000

Firstpage

689

Lastpage

692

Abstract

Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also provided by using the proposed model.

Keywords

VLSI; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; network routing; wiring; IC interconnects; VLSI; channel availability; channel routing; chip size limit; first metal level; multi-billion-transistor chips; multi-level interconnect network; physical via blockage model; signal interconnects; stochastic interconnect length distribution; wirability; wiring area; Chip scale packaging; Clocks; Delay effects; Design automation; Dielectrics; Routing; Signal analysis; Signal design; Stochastic processes; Wiring;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.902263

Filename

902263