Title : 
The design of the MGAP-2: a micro-grained massively parallel array
         
        
            Author : 
Gayles, Eric S. ; Kellihr, T.P. ; Owens, Robert M. ; Irwin, Mary Jane
         
        
            Author_Institution : 
Intel Corp., Folsom, CA, USA
         
        
        
        
        
        
        
            Abstract : 
The Micro-Grain Array Processor-2 (MGAP-2) is a two-dimensional SIMD array of 49152 fine-grain processors designed primarily for high-performance signal and image processing. Each processor can compute two arbitrary three-input Boolean functions, contains local RAM, and has additional logic for interprocessor communication. The MGAP-2 differs from existing fine-grain arrays in that it has a high degree of integration while incorporating processor level interconnect control. Each processor can independently select its communication direction. This allows a programmer to map algorithms onto the array in a more efficient manner than if the processors communicated in the standard SIMD fashion. Also, the MGAP-2´s processor level interconnect allows groups of processors to be clustered into larger computational units, making the basic computational units as powerful as they need to be for a given problem.
         
        
            Keywords : 
Boolean functions; VLSI; application specific integrated circuits; integrated circuit design; integrated circuit interconnections; microprocessor chips; parallel architectures; MGAP-2; Micro-Grain Array Processor-2; SIMD fashion; arbitrary three-input Boolean functions; computational units; fine-grain processors; interprocessor communication; local RAM; micro-grained massively parallel array; processor level interconnect control; two-dimensional SIMD array; Boolean functions; Clustering algorithms; Communication system control; Image processing; Process control; Process design; Programmable logic arrays; Programming profession; Signal design; Signal processing;
         
        
        
            Journal_Title : 
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on