A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface

Author

Lee, Seon-Kyoo ; Park, Seung-Jin ; Park, Hong-June ; Sim, Jae-Yoon

Author_Institution

Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea

Volume

46

Issue

3

fYear

2011

fDate

3/1/2011 12:00:00 AM

Firstpage

651

Lastpage

659

Abstract

This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); low-power electronics; sensors; CMOS; ENOB successive approximation ADC; analog-to-digital converter; conversion-step ADC; differential multistage VCDL; energy 21 fJ; input-referred noise reduction; low-noise time-domain comparator; offset reduction; power 1.3 muW; size 0.18 mum; static power consumption elimination; voltage 0.6 V; word length 10 bit; Analog-to-digital converter; comparator; sensor interface; successive approximation ADC;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2010.2102590

Filename

5703143