• DocumentCode
    1437851
  • Title

    Combining logic minimization and folding for PLAs

  • Author

    Hsu, Yu-Chin ; Lin, Youn-Long ; Hsieh, Hang-Ching ; Chao, Ting-Hai

  • Author_Institution
    Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    40
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    706
  • Lastpage
    713
  • Abstract
    The authors present an approach that combines logic minimization and folding for a programmable logic array (PLA). An efficient algorithm is proposed for optimal bipartite column folding. In the algorithm, the authors model the PLA personality matrix as a network and the bipartite PLA folding as a partitioning problem of that network. This folding algorithm is able to find optimal solutions for the benchmarks from the literature. The algorithm also substitutes product terms by their alternatives in order to find the one best suited for folding. The authors combine this algorithm and a logic minimization algorithm into a folding system. When comparing the results to those by a conventional approach, about one half of the benchmarks show area gain if product-term-alternatives exist
  • Keywords
    logic arrays; logic design; minimisation of switching nets; PLAs; algorithm; benchmarks; folding; logic minimization; optimal bipartite column folding; partitioning; personality matrix; programmable logic array; Chaos; Circuits; Logic design; Logic functions; Matrix decomposition; Minimization methods; Partitioning algorithms; Programmable logic arrays; Signal generators; Sparse matrices;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.90249
  • Filename
    90249