• DocumentCode
    1437914
  • Title

    Automatic test pattern generation with branch testing

  • Author

    Makki, Rafic Z. ; Bou-Ghazale, Silvio ; Tianshang, Chen

  • Author_Institution
    Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
  • Volume
    40
  • Issue
    6
  • fYear
    1991
  • fDate
    6/1/1991 12:00:00 AM
  • Firstpage
    785
  • Lastpage
    791
  • Abstract
    The authors present a test algorithm for finite state machines called branch testing. Based on branch testing, a design-for-test (DFT) method is proposed. Comparisons to other DFT methods show the method to be competitive relative to circuit overhead. A minimum set of paths containing all primary and internal gate-level input/output lines is found. Each of these paths is then sensitized so as to detect all single stuck-at faults. The authors demonstrated that the one-hot encoded FSMs can be easily and thoroughly tested via a simple algorithm. It is demonstrated that the use of scan paths is not necessary if a one-hot encoded state assignment is made. The synthesis and simulation resulting have shown that the package of one-hot encoding and branch testing constitutes a viable design and test approach
  • Keywords
    automatic testing; fault location; logic testing; branch testing; design-for-test; finite state machines; gate-level input/output lines; scan paths; simulation; stuck-at faults; test algorithm; Automata; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design for testability; Electrical fault detection; Encoding; Fault detection; Packaging;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.90257
  • Filename
    90257