An 8-b 100-MSample/s CMOS pipelined folding ADC

Author

Choe, Myung-Jun ; Song, Bang-Sup ; Bacrania, Kantilal

Author_Institution

Rockwell Int. Corp., Thousand Oaks, CA, USA

Volume

36

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

184

Lastpage

194

Abstract

Although cascading reduces the number of folders used in folding analog-to-digital converters (ADCs), it demands wider bandwidth. The pipelining scheme proposed in this work greatly alleviates the wide bandwidth requirement of the folding amplifier. The pipelining is implemented with simple differential-pair folders. The key idea is to use odd multiples of folders with distributed interstage track/holds cooperatively with an algorithm for coding and digital error correction for the nonbinary system. The pipelined folding ADC prototyped using 0.5-μm CMOS exhibits a differential nonlinearity (DNL) of ±0.4 LSB and an integral nonlinearity (INL) of ±1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm×1.2 mm in active area and consumes 165 mW at 5 V

Keywords

CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.5 micron; 165 mW; 5 V; 8 bit; CMOS pipelined folding ADC; bandwidth; coding algorithm; differential nonlinearity; differential-pair folder; digital error correction; distributed interstage track/hold; folding amplifier; integral nonlinearity; nonbinary system; Analog-digital conversion; Bandwidth; CMOS analog integrated circuits; Error correction codes; Image coding; Interpolation; Pipeline processing; Preamplifiers; Prototypes; Signal processing algorithms;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.902759

Filename

902759