DocumentCode
1438453
Title
2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3
Author
Lindfors, S. ; Länsirinne, M. ; Halonen, K.
Author_Institution
R. Inst. of Technol., Stockholm, Sweden
Volume
37
Issue
3
fYear
2001
fDate
2/1/2001 12:00:00 AM
Firstpage
150
Lastpage
151
Abstract
The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV
Keywords
BiCMOS integrated circuits; analogue-digital conversion; cellular radio; delta-sigma modulation; mixed analogue-digital integrated circuits; modulators; radio receivers; signal sampling; switched capacitor networks; 0.35 micron; 100 kHz; 2.7 V; 50 MHz; 81 dB; ADC; ASIC; BiCMOS process; GSM cellular phone; IF sampling ΔΣ modulator; IF section; SC type; analogue to digital conversion; frequency downconversion; radio receiver; switched-capacitor DS modulator;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010125
Filename
902780
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