Effects of buffer layer structure on polysilicon buffer LOCOS for the isolation of submicron silicon devices

The effects of a buffer layer structure on polysilicon buffered LOCOS were shown and analyzed. Sample wafers are classified into four groups to show the effect of the buffer layer structure. The structures of the four different buffer layers are monolayer polysilicon (typical), monolayer amorphous silicon (α-Si), double layer α-Si, and triple layer α-Si. Total buffer layer thickness of each structure is 60 nm. Structural analysis of the resultant samples was performed by using SEM, TEM, and SIMS. Sample with typical buffer structure shows not only rough surface morphology of bird´s beak region but microtrenchings. By adopting the triple layer α-Si buffer structure (20 nm/20 nm/20 nm), we obtained smooth edge morphology and no microtrenchings. Leakage current of n⁺-p junction diode and gate oxide breakdown voltage of each sample were measured to check the effect of the buffer structure on PBL. Sample with the triple layer α-Si buffer structure shows the lowest junction leakage and the best gate oxide breakdown voltage characteristics. The electrical characteristics of the samples were consistent with the structural results