Self-aligned control of threshold voltages in sub-0.2-μm MOSFETs

We propose a new method to control the threshold voltages (V_th) in sub-0.2 μm MOSFETs. The method suppresses V_th fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the V_th in numerous MOSFETs and show that our method can indeed suppress V_th fluctuations caused by variations in the fabricated gate length