• DocumentCode
    1438715
  • Title

    A compact pre- and post-stress I-V model for submicrometer buried-channel pMOSFETs

  • Author

    Chyau, Chwan-Gwo ; Jang, Sheng-Lyang

  • Author_Institution
    Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan
  • Volume
    45
  • Issue
    10
  • fYear
    1998
  • fDate
    10/1/1998 12:00:00 AM
  • Firstpage
    2167
  • Lastpage
    2178
  • Abstract
    In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data
  • Keywords
    MOSFET; carrier mobility; electron traps; hot carriers; semiconductor device models; semiconductor device reliability; I-V model; channel length modulation; channel shortening effect; circuit simulation; damaged channel region; degraded BC MOSFET model; drain current model; drain induced barrier lowering; forward-biased modes; gate voltage induced mobility degradation; hot-carrier-induced electron trapping; post-stress model; pre-stress model; quasi-two-dimensional approach; reverse-biased modes; series drain resistance; series source resistance; stress-time-dependent resistance; submicrometer buried-channel pMOSFETs; threshold voltage reduction; velocity saturation; Analytical models; Circuit simulation; Degradation; Displays; Electron traps; Hot carrier effects; Hot carrier injection; Hot carriers; MOSFETs; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.725251
  • Filename
    725251