DocumentCode
1438760
Title
Defect-oriented testing and defective-part-level prediction
Author
Dworak, Jennifer ; Wicker, Jason D. ; Lee, Sooryong ; Grimaila, Michael R. ; Mercer, M. Ray ; Butler, Kenneth M. ; Stewart, Bret ; Wang, Li C.
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Volume
18
Issue
1
fYear
2001
Firstpage
31
Lastpage
41
Abstract
After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis
Keywords
fault diagnosis; integrated circuit testing; logic testing; IC manufacturers; defect-oriented testing; defective-part-level prediction; stuck-at fault detection; test patterns; Circuit analysis; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit testing; Manufacturing industries; Predictive models; Production facilities; Silicon; Yield estimation;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.902820
Filename
902820
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