• DocumentCode
    143885
  • Title

    DAC for positron emission tomography front-end

  • Author

    Cruz, Hugo ; Ting-Chia Yeh ; Hong-Yi Huang ; Shueen-Yu Lee ; Ching-Hsing Luo

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2014
  • fDate
    11-14 April 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Positron emission tomography architectures have been traditionally dependent on zero crossing discriminators, external voltage references, or fixed voltage references with restricted voltage steps. This paper presents a digital-to-analog converter (DAC) utilized to set the threshold voltages of Time-of-Flight Positron Emission Tomography (TOF-PET) comparators. The DAC circuit uses a charge redistribution architecture, and all the required building blocks have been fully integrated in a 90 nm CMOS process with an area of 170 × 65 μm2. The power consumption is 324 μW with 1.2-V supply voltage. Using a 10-MHz clock, this DAC achieves an effective number of bits (ENOB) of 8.2.
  • Keywords
    CMOS integrated circuits; biomedical electronics; comparators (circuits); digital-analogue conversion; positron emission tomography; CMOS process; DAC circuit; ENOB; TOF-PET; charge redistribution architecture; digital-to-analog converter; effective number of bits; frequency 10 MHz; positron emission tomography front-end; power 324 muW; power consumption; size 90 nm; threshold voltages; time-of-flight positron emission tomography comparators; voltage 1.2 V; Bioinformatics; Capacitors; Positron emission tomography; Power demand; Simulation; Threshold voltage; Voltage measurement; Front-End; LNA; RF; back-gate; current-reuse; mixer;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bioelectronics and Bioinformatics (ISBB), 2014 IEEE International Symposium on
  • Conference_Location
    Chung Li
  • Print_ISBN
    978-1-4799-2769-2
  • Type

    conf

  • DOI
    10.1109/ISBB.2014.6820890
  • Filename
    6820890