Title :
A new compact neuron-bipolar junction transistor (νBJT) cellular neural network (CNN) structure with programmable large neighborhood symmetric templates for image processing
Author :
Wu, Chung-Yu ; Yen, Wen-Cheng
Author_Institution :
Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
1/1/2001 12:00:00 AM
Abstract :
Based on the basic device physics of the neuron-bipolar junction transistor (νBJT), a new compact cellular neural network (CNN) structure called the νBJT CNN is proposed and analyzed. In the νBJT CNN, both νBJT and lambda bipolar transistor realized by parasitic p-n-p BJTs in the CMOS process are used to implement the neuron whereas the coupling MOS resistors are used to realize the symmetric synapse weights among various neurons. Thus it has the advantages of small chip area and high integration capability. Moreover, the proposed symmetric νBJT CNN can be easily designed to achieve large neighborhood without extra interconnection. By adding a metal-layer optical window to the νBJT, the νBJT can be served as the phototransistor, and the νBJT CNN can receive optical images as initial state inputs or external inputs. The correct functions of the νBJT CNNs in noise removal, hole filling, and erosion have been successfully verified in HSPICE simulation. An experimental chip containing a 32×32 νBJT CNN and a 16 ×16 νBJT CNN with phototransistor design, has been designed and fabricated in 0.6-μm single-poly triple-metal n-well CMOS technology. The fabricated chips have the cell state transition time of 0.8 μs and the static power consumption of 60 μW/cell. The area density can be as high as 1270 cells/mm2. The measurement results have also confirmed the correct functions of the proposed νBJT CNNs
Keywords :
BiCMOS integrated circuits; SPICE; cellular neural nets; circuit simulation; image processing equipment; neural chips; programmable circuits; νBJT CNN; 0.6 micron; 0.8 mus; HSPICE simulation; area density; cell state transition time; cellular neural network structure; compact neuron-bipolar junction transistor; erosion; hole filling; integration capability; metal-layer optical window; noise removal; parasitic p-n-p BJTs; phototransistor design; programmable large neighborhood symmetric templates; single-poly triple-metal n-well CMOS technology; static power consumption; symmetric synapse weights; Bipolar transistors; CMOS process; CMOS technology; Cellular neural networks; Neurons; Optical interconnections; Optical noise; Phototransistors; Physics; Resistors;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on