DocumentCode :
1439991
Title :
A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects
Author :
Akrout, Chekib ; Bialas, John ; Canada, Miles ; Cawthron, Duane ; Corr, James ; Davari, Bijan ; Floyd, Robert ; Geissler, Stephen ; Goldblatt, Ronald ; Houle, Robert ; Kartschoke, Paul ; Kramer, Diane ; McCormick, Peter ; Rohrer, Norman ; Salem, Gerard ;
Author_Institution :
Microelectron. Div., IBM Corp., Austin, TX, USA
Volume :
33
Issue :
11
fYear :
1998
fDate :
11/1/1998 12:00:00 AM
Firstpage :
1609
Lastpage :
1616
Abstract :
This paper describes the performance improvements of a reduced instruction set computer (RISC) microprocessor that has migrated from a 2.5 V technology to a 1.8 V technology. The 1.8 V technology implements copper interconnects and low Vt field-effect transistors in speed-critical paths and has an Leff of 0.12 μm. Global clock latency and skew are improved by using copper wires, and early mode timings are improved by reducing clock skew and adding buffers. These enhancements, along with an environment of 2.0 V, 85°C, and with a fast process, produced a 480-MHz RISC microprocessor
Keywords :
CMOS digital integrated circuits; copper; integrated circuit interconnections; microprocessor chips; reduced instruction set computing; timing; 0.12 micron; 1.8 to 2 V; 480 MHz; 85 C; CMOS technology; Cu; Cu interconnects; RISC microprocessor; buffers; early mode timings; global clock latency improvement; low-threshold FETs; reduced instruction set computing; skew improvement; speed-critical paths; CMOS technology; Clocks; Copper; Frequency; Integrated circuit interconnections; Microelectronics; Microprocessors; Reduced instruction set computing; Tungsten; Wires;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.726544
Filename :
726544
Link To Document :
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