Title :
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
Author :
Heald, Raymond ; Shin, Ken ; Reddy, Vinita ; Kao, I-Feng ; Khan, Masood ; Lynch, William L. ; Lauterbach, Gary ; Petolino, Joe
Author_Institution :
Sun Microelectron., Palo Alto, CA, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way set-associative cache. This address adder avoids time-consuming carry propagation by using an A+B=K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-μm process, This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access
Keywords :
CMOS memory circuits; cache storage; decoding; random-access storage; 0.25 micron; 1.6 ns; 2.6 ns; 512 Kbit; 64 KByte; CMOS RAM; address adder; decode structure; delayed-reset logic; four-way set-associative cache; sum-addressed-memory cache; wave pipelined RAM; Added delay; Adders; Assembly; Circuits; Decoding; Equations; Logic; Read-write memory; Testing; Throughput;
Journal_Title :
Solid-State Circuits, IEEE Journal of
