Author :
Eto, Satoshi ; Matsumiya, Masato ; Takita, Masato ; Ishii, Yuki ; Nakamura, Toshikazu ; Kawabata, Kuninori ; Kano, Hideki ; Kitamoto, Ayako ; Ikeda, Toshimi ; Koga, Toru ; Higashiho, Mitsuhiro ; Serizawa, Yuji ; Irabashi, K. ; Tsuboi, Osamu ; Yokoyama, Yu
Abstract :
This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (Vss) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-Vcc precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing ±20-ps quantization errors for clock recovery and skew elimination
Keywords :
DRAM chips; clocks; delay circuits; memory architecture; 1 Gbit; 2.1 V; SDRAM; cell-operating concept; clock recovery; delay-locked-loop circuit; ground-level precharged bit line; negative word-line reset scheme; nonboosted word line; power consumption; quantization errors; skew elimination; synchronous DRAM; Circuits; Clocks; Degradation; Delay; Energy consumption; Low voltage; Quantization; Random access memory; SDRAM; Threshold voltage;
