Title :
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
Author :
Kirihata, Toshiaki ; Gall, Martin ; Hosokawa, Kohji ; Dortu, Jean-Marc ; Wong, Hing ; Pfefferi, P. ; Ji, Brian L. ; Weinfurtner, Oliver ; DeBrosse, John K. ; Terletzki, Hartmud ; Selz, Manfred ; Ellis, Wayne ; Wordeman, Matthew R. ; Kiehl, Oliver
Author_Institution :
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
A 220-mm2, 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC4 current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead
Keywords :
CMOS memory circuits; DRAM chips; pipeline processing; redundancy; 0.22 micron; 0.484 micron; 13.5 ns; 135 MHz; 256 Mbit; 270 Mbit/s; 5 ns; 86.7 percent; 90 mA; CMOS technology; SDRAM; address-access time; asymmetric block activation; buried strap trench cell; burst frequency; cell/chip-length efficiency; chip overhead; clock-access time; divided column redundancy scheme; eight-bank organizations; four-bank organizations; frequency doubling test mode; intraunit address increment pipeline; seamless burst operation; selectable row domain; shared row decoders; shmoo analysis; single ended read-write-drive bus; single-ended addresses; single-sided stitched WL architecture; CMOS technology; Decoding; Frequency; Logic arrays; Pipelines; Random access memory; Redundancy; SDRAM; Solid state circuit design; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
