DocumentCode :
1440117
Title :
Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory
Author :
Tertinek, Stefan ; Gleeson, James P. ; Feely, Orla
Author_Institution :
Dept. of Electr., Electron. & Mech. Eng., Univ. Coll. Dublin, Dublin, Ireland
Volume :
57
Issue :
9
fYear :
2010
Firstpage :
2367
Lastpage :
2380
Abstract :
Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear due to the hard nonlinearity introduced by the binary phase detector (BPD). This paper provides an exact statistical analysis of the steady-state timing jitter in a first-order BBPLL when the reference clock is subject to accumulative jitter. By elaborating on the analogy of viewing a first-order BBPLL as a single-integration delta modulator (DM) in the phase domain, we are able to relate hunting jitter and slew-rate limiting in a BBPLL to granular noise and slope overload in a DM. The stochastic timing-jitter behavior is modeled as a sign-dependent random walk, for which we obtain the asymptotic characteristic function and analytical expressions for the first four cumulants. These expressions are applied to the BBPLL to statistically analyze the static timing offset and the rms timing jitter, including the effect of a frequency offset. The analysis shows that the rms timing jitter is constant for small rms clock jitter and grows quadratically with large rms clock jitter, and that there exists an optimal bang-bang phase step for minimum rms timing jitter. Computing the kurtosis reveals the effect of the BPD nonlinearity: The timing jitter is largely non-Gaussian.
Keywords :
clocks; delta modulation; phase locked loops; statistical analysis; timing jitter; accumulative jitter; binary phase detector; delta modulator; first-order bang-bang phase-locked loops; reference clock; sign-dependent random-walk theory; statistical analysis; steady-state timing jitter; Clocks; Delta modulation; Detectors; Phase detection; Phase locked loops; Phase modulation; Phase noise; Statistical analysis; Steady-state; Timing jitter; Bang-bang phase-locked loop (BBPLL); cumulants; delta modulator (DM); kurtosis; sign-dependent random walk (SDRW); timing jitter;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2010.2043016
Filename :
5430899
Link To Document :
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