Title :
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing
Author :
Igura, Hiroyuki ; Naito, Yukihiro ; Kazama, Kenya ; Kuroda, Ichiro ; Motomura, Masato ; Yamashina, Masakazu
Author_Institution :
Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
fDate :
11/1/1998 12:00:00 AM
Abstract :
This paper presents a newly developed parallel digital signal processor (DSP) for mobile multimedia processing. The DSP achieves 800 MOPS at 110 mW (1.5 V) through its task-parallel processing on four DSP cores. The parallel architecture, including data sharing and synchronization mechanisms, is carefully designed to be hardware and power efficient for portable multimedia applications. By using the parallel processing architecture, clock gating, and other low-power methods, about 85% power reduction is achieved. The 9.2-mm-square die contains 5.2-M transistors with 0.25-μm CMOS process
Keywords :
CMOS digital integrated circuits; digital signal processing chips; multimedia computing; parallel architectures; portable computers; 0.25 micron; 1.5 V; 110 mW; CMOS process; clock gating; data sharing; low-power methods; mobile multimedia processing; parallel DSP; parallel architecture; synchronization mechanisms; task-parallel processing; Clocks; Digital signal processing; Digital signal processing chips; Digital signal processors; Energy consumption; Laboratories; National electric code; Parallel processing; Signal processing; Synchronization;
Journal_Title :
Solid-State Circuits, IEEE Journal of
