Title :
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter
Author :
Matsuura, T. ; Nara, Takaaki ; Komatsu, Teruhisa ; Imaizumi, E. ; Katsu, H. ; Sato, Kiminori
Author_Institution :
Semicond. & Integrated Circuits Div., Hitachi Ltd., Tokyo
fDate :
11/1/1998 12:00:00 AM
Abstract :
A 3.3-V, 1-W, 240-Mbps extended-partial-response maximum-likelihood read/write-channel large-scale-integration chip for hard disk drives has been developed. Power consumption of 1 W was achieved by using a 3.3-V power supply, a 0.4-μm CMOS process, and a 3.3-V CMOS analog circuit design. Our approach to achieving a high transfer rate of 240 Mbps was to develop an interleaved subranging pipeline lookahead analog/digital (A/D) converter architecture. The power consumption of this A/D converter is 200 mW at 255 MHz. The read-mode channel path combines an acquisition-mode analog phase-locked loop (PLL) and a tracking-mode precision digital PLL, enabling the use of a long-latency pipeline A/D converter in the digital PLL. Consequently, a bit error rate of 10**(-9) at a signal-to-noise ratio of 24.5 dB has been achieved
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital phase locked loops; hard discs; large scale integration; maximum likelihood detection; partial response channels; 0.4 micron; 1 W; 200 mW; 240 Mbit/s; 255 MHz; 3.3 V; CMOS process; EPRML; analog circuit design; bit error rate; extended-partial-response maximum-likelihood; hard disk drives; interleaved subranging pipeline A/D converter; long-latency pipeline A/D converter; power consumption; read-channel LSI chip; read-mode channel path; signal-to-noise ratio; tracking-mode precision digital PLL; transfer rate; Analog circuits; Analog-digital conversion; CMOS analog integrated circuits; CMOS process; Energy consumption; Hard disks; Large scale integration; Phase locked loops; Pipelines; Power supplies;
Journal_Title :
Solid-State Circuits, IEEE Journal of
