Abstract :
Trace cache is a new instruction supply mechanism for wide-issue superscalar processors. It caches dynamic instruction traces, each of which consists of multiple basic blocks. As a result, a number of basic blocks are combined into a single large unit, and hence the effective fetch bandwidth is enlarged. The trace cache has been evaluated only on much aggressive superscalar processors. However, an efficient instruction supply mechanism is required also for moderate-scale processors, as media-specific applications increase their importance. The paper evaluates the trace cache fetch mechanism on moderate-scale superscalar processors. A simpler trace cache is proposed, named nonconsecutive basic block buffer (NCB), for the processors. From experimental evaluation, using the NCB improves the instruction supply efficiency by approximately 10% and hence processor performance is also improved by approximately 10% for integer programs
