Title : 
A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method
         
        
            Author : 
Joo, Hye-Yoon ; Kim, Lee-Sup
         
        
            Author_Institution : 
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
         
        
        
        
        
            fDate : 
3/1/2010 12:00:00 AM
         
        
        
        
            Abstract : 
This brief presents a data-pattern-tolerant adaptive equalizer using the spectrum balancing method. In addition to a high-frequency boost control loop, this equalizer has a corner frequency control loop to guarantee its accurate adaptation for various data patterns and data rates. Measured results show that the jitter of the eye is reduced by a maximum of 37% when compared to the previous spectrum balancing equalizer. The chip is fabricated in a 0.18-??m CMOS process, and the equalizer core occupies 0.35 mm2 and consumes 85 mW.
         
        
            Keywords : 
CMOS integrated circuits; adaptive equalisers; frequency control; CMOS process; data-pattern-tolerant adaptive equalizer; equalizer core; frequency control loop; high-frequency boost control loop; power 85 mW; size 0.18 mum; spectrum balancing equalizer; spectrum balancing method; Adaptive equalizer; channel loss; data pattern; intersymbol interference (ISI);
         
        
        
            Journal_Title : 
Circuits and Systems II: Express Briefs, IEEE Transactions on
         
        
        
        
        
            DOI : 
10.1109/TCSII.2010.2040309