Title :
Worst-case bias during total dose irradiation of SOI transistors
Author :
Ferlet-Cavrois, V. ; Colladant, T. ; Paillet, P. ; Leray, J.L. ; Musseau, O. ; Schwank, J.R. ; Shaneyfelt, M.R. ; Pelloie, J.L. ; du Port de Poncharra, J.
Author_Institution :
CEA, Centre d´´Etudes de Bruyeres-le-Chatel, France
fDate :
12/1/2000 12:00:00 AM
Abstract :
The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide
Keywords :
MOSFET; X-ray effects; silicon-on-insulator; buried oxide; charge trapping; partially depleted SOI transistor; threshold voltage; total dose irradiation; worst-case bias; Analytical models; Circuit testing; Computational modeling; Laboratories; Military computing; Radiation hardening; Silicon on insulator technology; Space technology; Substrates; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
