DocumentCode :
1441378
Title :
Full-MOSFET mixed-mode duty cycle corrector
Author :
Wu, J.H. ; Gu, J.H. ; Zhang, L.Z. ; Zhang, M.
Author_Institution :
National ASIC Research Center, Southeast University, Nanjing, 210096, People´s Republic of China
Volume :
47
Issue :
19
fYear :
2011
fDate :
7/3/1905 12:00:00 AM
Firstpage :
1067
Lastpage :
1069
Abstract :
A novel mixed-mode 50% duty cycle corrector (DCC) based on a digital process is proposed. The DCC adopts both digital and analogue correction methods in which a half cycle delay line is used for coarse correction, and an analogue feedback loop based on full-MOSFETs for further fine tuning to achieve fast settling and high precision. The rising edge of the output clock has a constant delay compared to the input clock, which makes the DCC easy to cooperate with a delay locked loop. Simulated results using 0.13 μm CMOS technology show that the output duty cycle is corrected to 50±0.22% throughout the input duty cycle range from 20 to 80% in the frequency range 200 MHz-2 GHz.
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el.2011.1660
Filename :
6146219
Link To Document :
بازگشت