Title :
Clock buffer circuit soft errors in antifuse-based field programmable gate arrays
Author :
Wang, Jih-Jong ; Katz, Richard B. ; Dhaoui, Fethi ; McCollum, John L. ; Wong, Wayne ; Cronquist, Brian E. ; Lambertson, Roy T. ; Hamdy, Esmat ; Kleyner, Igor ; Parker, Wanida
Author_Institution :
Actel Corp., Sunnyvale, CA, USA
fDate :
12/1/2000 12:00:00 AM
Abstract :
Three-dimensional mixed-mode device simulation is used to investigate the clock upset in an antifuse FPGA device. Two versions of the clock circuit were simulated, the original and the redesigned with improved SEU hardness. The threshold LET of each version was simulated both at static and during transition. Compared to the test data, the simulated results consistently underestimate the LETth. The difference between LETth at static and during transition is relatively small. This disagrees with the previous speculation that the clock upset is due to heavy-ion strikes very close to the clock edge. Efforts were also made to optimize the simulation methodology to reduce the simulation time for practicality
Keywords :
buffer circuits; circuit simulation; field programmable gate arrays; ion beam effects; logic simulation; radiation hardening (electronics); SEU hardness; antifuse-based field programmable gate arrays; clock buffer circuit; clock upset; heavy-ion strike; simulation time; soft errors; three-dimensional mixed-mode device simulation; threshold LET; Circuit simulation; Circuit testing; Clocks; DH-HEMTs; Field programmable gate arrays; Optimization methods; Programmable logic arrays; SPICE; Single event upset; Ultra large scale integration;
Journal_Title :
Nuclear Science, IEEE Transactions on
