Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Author

Zjajo, Amir ; Barragan, Manuel J. ; De Gyvez, José Pineda

Author_Institution

Delft Univ. of Technol., Delft, Netherlands

Volume

61

Issue

8

fYear

2012

Firstpage

2212

Lastpage

2221

Abstract

This paper reports design, efficiency, and measurement results of the process variation and temperature monitors for yield analysis and enhancement in deep-submicron CMOS circuits. Additionally, to guide the verification process with the information obtained through monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier are proposed. The monitors and algorithms are evaluated on a prototype 12-bit analog-to-digital converter fabricated in standard single poly six-metal 90-nm CMOS.

Keywords

CMOS integrated circuits; analogue-digital conversion; electronic engineering computing; expectation-maximisation algorithm; integrated circuit design; integrated circuit measurement; optimisation; pattern classification; support vector machines; analog-to-digital converter; deep-submicron CMOS circuit; expectation-maximization method; low-power die-level process variation; optimization; size 90 nm; standard single polysix-metal CMOS circuit; support vector machine classifier; temperature monitoring; verification process; word length 12 bit; yield analysis; Current measurement; Detectors; Monitoring; Resistors; Temperature measurement; Temperature sensors; Transistors; Analog test; process variation monitoring; temperature monitors; yield enhancement;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/TIM.2012.2184195

Filename

6146431